Hardware Implementation of Adaboost-based Sign Recognition for Miniature Robot
Yutaka Usui, Katsuya Kondo · Hokkaido University Collection of Scholarly and Academic Papers (Hokkaido University) · 2009
In this paper, we propose a hardware implementation of a sign recognition system for miniature robot based on Adaboost algorithm. We describe the hardware design techniques including preprocessing, pipelined feature generator and classifier processing. The proposed pipelined architecture reduces working memory significantly compared to straightforward implementation that requires large frame memory. The architecture has been designed by using System Verilog and Verilog-HDL. Implementation result shows that FPGA lcell usage of Altera Cyclone-III(EP3C55F) is 44%. Evaluation result shows that the error rate is 6% or less, and processing time is within video frame rate.