Floating Point HUB Adder for RISC-V Sargantana Processor
Gerardo Bandera, Javier Salamero, Miquel Moretó, Julio Villalba · arXiv (Cornell University) · 2024
HUB format is an emerging technique to improve the hardware and time requirement when round to nearest is needed. On the other hand, RISC-V is an open-source ISA that many companies currently use in their designs. This paper presents a tailored floating point HUB adder implemented in the Sargantana RISC-V processor.