MAO: Memory Architecture Obfuscation
Sun Tanaka, Shinya Takamaeda-Yamazaki · 2023
Hardware obfuscation is a promising method to protect hardware intellectual property (IP) against threats posed by the globalized supply chain and prevent accidental IP infringement. Especially in modern IP cores such as deep neural network accelerators, on-chip memories are essential components for efficiency, and on-chip memory architecture itself is an important intellectual property within an IP. With memory architecture information, such as the number of memories, their bit widths and depths, and their connections, an adversary can deduce the hardware algorithm and dataflow behind the circuit. Memory architecture should be obfuscated, as well as the random logic circuit, to hide essential information about IPs. While various obfuscation techniques for general random logic of combinational circuits and flip-flops have been proposed, the circuit benchmarks utilized in their evaluations do not include on-chip memories. Thus, hiding the on-chip memory architecture is not considered well in the literature. In this paper, we propose a novel concept of memory architecture obfuscation and provide a method to realize it. The proposed method conceals the memory architecture by bringing uniformity to memory representations. Our method offers a new option for IP providers to prevent troubles in IP resource distribution. We develop a prototype obfuscation tool and evaluate the overhead of the proposed method on multiple IPs. We discuss the experimental results and present obfuscation strategies. IP providers can determine the preferable obfuscation intensity of the proposed method according to their performance demands.