Learning Your Lock: Exploiting Structural Vulnerabilities in Logic Locking
Prabuddha Chakraborty, Jonathan Cruz, Rasheed Almawzan, Tanzim Mahfuz, Swarup Bhunia · IEEE Design and Test · 2024
The decentralized semiconductor supply chain is vulnerable to different security threats such as intellectual property (IP) theft and malicious modifications. Logic locking (LL) can be used to secure digital designs from some of these threats and is typically carried out by inserting a set of logic gates/flops in the design such that the design can only be operated with the right key or key sequence. However, many LL techniques have been shown to be vulnerable to learning guided structural attacks such as SAIL. The goal of this work is to demonstrate the versatility, extensibility, and wide applicability of SAIL towards reinforcing the need for structural security in LL.