Exploring Challenges Associated with Employing SmartNICs as General-Purpose HPC Accelerators
Brody Williams, Yong Chen, Wendy Poole, Steve Poole · 2023
Galvanized by waning general-purpose CPU per-formance improvements, large-scale system architectures have shifted towards increasingly heterogeneous designs in recent years. Systems devised under this regime are constructed using the principles of hardware/software codesign and incorporate domain specific accelerators in order to optimize system per-formance for targeted use cases. In this context, smartNICs represent a class of accelerator devices currently experiencing a resurgence. In the past, power and flexibility limitations largely relegated these devices to performing only tasks associated with low-level networking operations. More recent smartNIC incarnations have addressed many of these design constraints. The full range of capabilities of these new smartNICs, however, is not well understood. Moreover, the suitability of these devices as general-purpose accelerators, particularly within the high performance computing domain, as well as any potential barriers to their more widespread adoption, remain to be seen. In this work, we detail our efforts to explore these open questions.