A New Framework for RTL Test Points Insertion Facilitating a “Shift-Left DFT” Strategy
Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Oussama Laouamri, Naveen Khanna, Jeff Mayer, Nilanjan Mukherjee · 2023
This paper proposes a new framework for inserting test points at RTL (Register Transfer Level) enabling better Power-Performance-Area-Testability (PPAT) optimization during synthesis and yielding quick turn-around time and faster Time-to-Market (TTM). It introduces the concept of editable nodes in RTL designs and avoids locations that are difficult to modify. Early identification of editable nodes in the RTL to guide and drive the test point analysis engine helps in improving the quality of test points inserted into the design. In addition, the proposed methodology involves optimization of the RTL, a quick synthesis of the design, and test point analysis at the netlist-level by avoiding locations that are pre-marked as ‘don't-touch’. Once the test point locations are identified in an internal unmapped gate representation, they are back annotated and inserted in the RTL. Some locations can be directly mapped back, whereas some other locations can be mapped back to expression and sub-expression boundaries in RTL with the help of additional information that is exported during the logic synthesis step. Experimental results on several industrial designs show that the effectiveness of test points inserted at RTL closely matches their counterparts at the gate-level with added benefits of better area, timing, test coverage, and pattern count optimization early in the design flow.