A Testbench for Stereo-Processing Acceleration Based on PYNQ and the StereoPi
John A. Kalomiros, John V. Vourvoulakis, Stavros D. Vologiannidis · 2023
Stereo processing accelerators are often designed and implemented using Field Programmable logic. In this paper, a new setup for the implementation and practical testing of hardware stereo-processing solutions is presented. A PYNQ Z1 board featuring a Zynq SoC is combined with a low-cost StereoPi camera. It is shown that the system is versatile, since it can exploit the optimized OpenCV capabilities of the Raspberry Pi Compute Module for image pre-processing and the hardware acceleration capabilities of the Programmable Logic embedded in the Zynq chip. A series of experiments prove the feasibility of the concept. A state-of-the-art implementation of the SGM stereo algorithm in hardware description language is used in order to prove the feasibility of the design. The system can process depth maps with the nominal refresh rate of 60 fps, using stereo image resolution 640×480 and up to 96 levels of disparity.