Simulation Improvements, Challenges & Solutions While Using DTL, Signal Access & DebuggerDB Optimization, PC, TC, Save-Restore
Sourabh Saluja, Yaswani Priyanka Vempali, Syed Kamil Hussain Samnani, Joe Manzella, Harbaksh Mangat, Vineet Kumar Dubey, Prabahar Krishna Gounder, Ankit Gopani · 2023
Every new generation of large System-on-Chip designs brings with it new challenges for verification and design teams as more logic blocks are packed for more features and overall product performance. This emphasizes the importance of the design verification team's capacity to achieve both the strict coverage requirements and tape-out schedules. Therefore, anything that can be done to speed up the compile & simulation and to thus shorten the Turnaround Time for both the individual tests and the entire regression suite is very beneficial. In the current work, we present the analysis of selected compile and simulation methodologies - Dynamic Test Loading, Signal Access Optimization, Debugger Database Optimization, Partition Compile, Turbo Compile and Save-Restore. We also share the Turnaround Time improvements and compute resource reductions on two complex SoCs along with the challenges faced in utilizing these methodologies and the solutions to overcome those challenges.