Physical Unclonable Function Chip based on SOT-MRAM in 180 nm CMOS Technology
Luyao Shi, Zhengyi Hou, Tianrui Guo, Pengbin Li, Chuanpeng Jiang, Kaihua Cao, Zhaohao Wang, Weisheng Zhao, Wang Bi · 2023
This paper presents a 1 kb physical unclonable function (PUF) chip fabricated in a 180-nm CMOS process. The chip consists of in-plane magnetic anisotropy spin-orbit torque (IMA-SOT) PUF arrays and the necessary periphery circuits, which utilizes the manufacturing process deviation of common state of SOT devices to generate the randomness. Moreover, a dual-mode logic control design with a self-write back circuit is proposed to implement the transition between PUF and memory functions, which improves the flexibility and reliability of the PUF chip. The self-write back circuit is activated after reading the challenge-response pairs (CRPs), which can induce to the complementary states of SOT devices. The uniformity, uniqueness and reliability are experimentally measured by a comprehensive pretest procedure, and the inter- and intra-hamming distances are computed. Additionally, the SOT-PUF chips are subjected to repeated read testing at varying temperature and supply voltages to evaluate the stability under different operating conditions. This work provides a feasible approach for the preparation of highly integrated PUF chips based on SOT devices, offering a promising solution for secure hardware authentication applications.