Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology
Max Doblas, Gerard Candón, Xavier Carril, Marc Domínguez, Enric Erra, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradı́s, Jonnatan Mendoza, Josep Angel Oltra, Julián Pavón, Marco A. Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas · 2023
This paper describes the Sargantana System on chip (SoC), a 64-bit RISC-V single core processor designed by a number of academic institutions and manufactured in 22 nm FDSOI technology: BSC, UPC, UB, UAB, CIC-IPN and IMB-CNM (CSIC). The SoC includes the processor as well as, among other components, a Phase Locked Loop (PLL) operating up to 2 GHz, interfaces to HyperRAM and a Serdes up to 8 Gbps. The processor has demonstrated experimental correct operation at 800 MHz.