Simplifying RTL design and verification in chip manufacturing: A paradigm for Electronics Teaching using Open-Source tools
José Galeas, José-Borja Castillo-Sánchez, Martín González-García · 2023
This document introduces a wide-spreading project that allows engineering students to design, simulate, verify and manufacture a custom RTL design using HDL languages alongside a RISC-V core. To solve the deficiencies regarding functional core verification that this project features, this paper proposes the adoption of UVM and Python-based verification tools.