Accelerating Blake3 in RISC-V
Xiaofeng Zou, Yuanxi Peng, Tuo Li, Lingjun Kong, Zhaochun Pang, Lu Zhang · 2023
This paper proposes a novel hardware design to accelerate the Blake3 hash algorithm, a cryptographic hash function, on RISC-V architecture, using both vector extension (V1.0) and a specially designed Blake3 instruction. The design leverages the parallelism and simplicity of BLAKE3 to achieve high throughput and low latency, implementing the core compression function using a custom instruction set architecture that supports vector operations and constant computing. The Blake3 compression function is speed up in architecture based on hardware/software co-design. The design achieves a speed-up of 10 times for the compression function compare with a single core of 2.7GHz Xeon 8280 and 10% faster than an AVX512 implementation.