Testing and synthesis of systems -on -a -chip with unimplemented blocks.
HyungWon Kim · Deep Blue (University of Michigan) · 1999
Complex digital systems are increasingly being manufactured on a single integrated circuit referred to as a system-on-a-chip (SOC). SOCs make extensive use of pre-designed and verified intellectual Property (IP) circuits, also known as cores, which are obtained from various sources. IP circuits are difficult to test due to their hidden implementation details. The goal of the research presented in this thesis is to analyze the fundamental testing problems of SOCs and develop practical solutions for them. Conventional test methods, which target specific low-level (logic gate) realizations, cannot handle the testing of IP-based SOCs. This thesis proposes a realization-independent approach to SOC testing, which can generate efficient tests using only high-level functional models of the IP circuits. It also develops novel delay abstraction and associated testing methods that can verify the signal propagation delays of multi-block paths in SOCs, an important but little-studied testing problem. The key to our realization-independent testing approach is a powerful functional fault model based on universal tests derived from a circuit's high-level block structure. This fault model is used to construct a test generation technique that ensures exceptionally high coverage of faults in a broad range of implementations of the target circuit. A design-for-test method is also developed to synthesize a block structure of an arbitrary circuit that leads to realization-independent test sets of practical size. New delay testing methods for SOCs are proposed, which are based on novel test access (scan) and delay abstraction techniques. The scan technique enables any path passing through IP circuits to be sensitized for test purposes, while the delay abstractions creates symbolic delay models for IP circuits that can be used to compute tests for all paths of a specified delay range in an SOC. To compute a set of practical delay tests, efficient algorithms are developed, which use only the symbolic delay models, and thus protect the intellectual-property contents of the IP circuits. We have implemented the foregoing methods in computer programs, and conducted an extensive set of experiments to evaluate them using various benchmark circuits. The experiments confirm that our realization-independent testing approach can achieve complete coverage of standard stuck-at faults over a broad range of implementation styles. They also demonstrate that the proposed delay testing methods can test all target complete paths in SOCs efficiently.