A Hierarchical Dataflow Architecture for Large-Scale Multi-FPGA Biophysically Accurate Neuron Simulation
He Zhang · River Publishers eBooks · 2022
This chapter proposes an efficient, hierarchical dataflow architecture for large-scale biophysically accurate multichip implementation of the neural network. It summarizes the inter-connection network and SerDes interface and discusses the performance with different constraints. The chapter gives the implementation of the router in SystemC simulation and SerDes interface in VHDL. It discusses the simulation results. Mesh topology with multicast communication offers improved performance in comparison to fat-tree, point-to-point, and shared bus communication for neural networks in completed and random connection. In the simulator, both unicast and multicast routings supported with different allocator structure in the mesh routers. The communication architecture is responsible for initializing and delivering requested packet containing the dendrite or axon potential to the calculation architecture, and communication to an external interface outside of the proposed design. Biophysically accurate models of biological systems, such as the ones using the Hodgkin-Huxley formalism, are composed mostly of a set of computationally challenging differential equations often implementing an oscillatory behavior.