Dynamic Digital Circuit Locking (DDCL): A Shield against Static Analysis Attacks
Ye Ziyang, Makoto Ikeda · 2023
With the rise of the fabless business model, security threats, including Intellectual Property (IP) theft, overproduction, counterfeiting, and reverse engineering, have increased. This paper introduces Dynamic Digital Circuit Locking (DDCL) as a method to counteract these threats. At its core, DDCL utilizes dynamic logic gates for locking. These gates mimic the operation of standard logic gates through a dynamic process, thereby exploiting adversaries who depend on static digital circuit analysis. As a result, DDCL can resist all static analysis attacks more effectively than conventional techniques. DDCL surpasses earlier methods by its reliance on logic loops for proper operation, which makes loop breaking attacks less effective. However, the advanced security offered by DDCL also presents challenges, such as increased power consumption and circuit complexity. This paper further examines the structure, security aspects, and comparative performance of DDCL. It underscores its value in multi-vendor scenarios and its compatibility with existing IP cores, which require only minor changes to original designs, thereby illustrating the practical role of DDCL in enhancing hardware security.