Educational Simulator for Analysing Pipelined LEGv8 (subset of ARMv8)Architecture
Jia Tian Chia, K. G. Smitha · 2023
This paper presents the design and implementation of a pipelined Lessen Extrinsic Garrulity (LEGv8) architecture simulator, subset of ARMv8 architecture. The simulator is developed as a web application that can simulate the assembly of instructions in the LEGv8 assembly language, the execution of the instructions, and the visualisation of data path during execution. The simulator supports both single cycle and pipelined execution, with the option to select the control and data hazard handling methods to use. Users will be able to analyse the changes in the registers and memory, branching behaviour, hazard detection and elimination, as well as visualise data flow when stepping through instructions. This gives users the freedom to comprehend computer architecture more easily at their own pace by making use of the user-friendly and interactive educational simulator to enhance their understanding beyond what can be taught in the classroom.