Security Verification of RISC-V System Based on ISA Level Information Flow Tracking
Lingjuan Wu, Yifei Gao, Jiacheng Zhu, Yu Tai, Wei Hu · 2023
Software attacks that exploit the hardware security vulnerabilities of processors have become new breakthrough points for hackers, which pose severe threats to hardware security and trust. This paper proposes a novel system security verification method based on instruction set architecture (ISA) level information flow tracking (IFT), which is capable of modeling and checking security properties in both software and hardware designs. We use RISC-V system as a demonstration, which is a lately developed open-source ISA widely used in Internet of Things and is facing severe security threats due to the universal interconnection of devices. By developing RISC-V software and hardware IFT models, security properties including confidentiality and integrity can be verified and vulnerabilities can be detected. Experimental results show that the proposed verification method can detect software security threats and hardware security vulnerabilities in the RISC-V processor design.