Test Pattern Reduction Using Various ML Algorithms
C S Anirudhra, Bhavya Reddy, Himavanth Ravindran Kammari, Vattikuti Bhanu Sahithya, J. P. Anita · 2023
This paper presents the integration of using ML models with fault simulation to reduce the test volume in VLSI testing. It introduces a novel approach to VLSI testing, focusing on reducing the test volume while maintaining high test coverage. It has an upper edge when compared with the traditional testing as the test cost reduces drastically. Experimental results show an average of 30% test pattern reduction is possible