Design of CNTFET-based ternary logic flip-flop and counter circuits using unary operators
Trapti Sharma · 2023
Today’s era of smart electronics demands primarily compact high computational systems with reduced power overhead and high energy efficiency. However, digital computation using radix two and CMOS technology has reached saturation limits for the implementation of logic functions in digital system design. Multi-valued logic design offers an effective remedy to reduce power overhead components primarily due to the wire interconnects within a chip area. Flip-flops are basic sequential elements that are employed in various digital applications such as counters, registers, frequency dividers, etc. This chapter presents three-valued flip-flop and counter cells realized utilizing unary operators. Initially, single-shift and dual-shift operators are designed by taking the average of two unary literals and exploiting efficient voltage divider topology. Then master-slave D-flip-flop design realization is performed by cascading proposed shifting literals instead of conventional inverter circuits. Further, to illustrate the applicability of suggested D-flip-flops in complex designs, they are combined to form counter structures. Ternary logic benefits of increased processing capability with a fewer flip-flop cells count result in power savings with fewer clock inputs as compared to binary logic counters. For the performance assessment of the proposed designs, Synopsys HSPICE simulations are conducted considering the 32-nm CNTFET Stanford model. Experimental results demonstrate the superiority of proposed counter and flip-flop designs with regard to power consumption and energy consumption in comparison to recent counterpart. Hence multi-valued logic design benefits of enhanced computation capability and reduced power overhead due to interconnects, as well as lesser clock inputs, are utilized in the VLSI circuit’s realization.