Exploiting Feature Layer for Read Reference Voltage Optimization on 3-D NAND Flash Memory
Debao Wei, Zhelong Piao, Ming Liu, Yanlong Zeng, Hua Feng, Liyan Qiao, Xiyuan Peng · IEEE Transactions on Consumer Electronics · 2023
Three-dimensional (3D) NAND flash memories have been widely employed as non-volatile memory mediums in modern consumer electronics. However, the adoption of 3D structures also induces complex reliability issues in flash memories. Read reference voltage (RRV) optimization is regarded as one of the key fundamental techniques to enhance the reliability of flash-based storage. Conventional strategies generally utilize the samples extracted layer-by-layer from the target flash block to estimate the optimal read voltage, resulting in significant read latency. In this work, we propose utilizing the feature layer concept to diminish the sampling overhead caused by RRV optimization, where the optimal read voltages at block granularity (BGVI) or layer granularity (LGVI) are inferred through samples extracted from the feature layer. We further develop a noise-reduction optimal read voltage determination algorithm (NRVD) to overcome the measurement noise existing in samples extracted from the feature layers. Experiments on real flash chips demonstrate that the proposed design can infer the optimal read voltages with considerable accuracy and decrease the read count by more than 50% compared with the existing RRV optimization designs.