On Attacking Scan-based Logic Locking Schemes
Govind Rajhans Jadhav, Sonali Shukla, Virendra Pal Singh · 2023
Logic Locking provides promising protection to safeguard hardware Intellectual Properties (IPs) against IP piracy and IP overproduction. However, numerous attacks have been proposed to compromise the security of logic-locked combinational circuits by retrieving their secret key. An attacker can also exploit the test interfaces of the chip to extract the secret key of the logic-locked sequential circuits. To combat such threats, scan access protection techniques used in conjunction with functional logic locking techniques to provide promising solutions known as scan-based logic locking schemes. However, this paper demonstrates an attack scenario where a malicious circuitry inserted by an untrusted foundry can effectively bypass the scan-blockage based locking defense strategies. This in turn, allows the SAT attack to defeat functional logic locking easily. To mount an attack, a light-weight and difficult to detect Trojan circuit is developed. Further, the proposed Trojan circuit is inserted in the locked ITC’99 benchmark circuits to justify its low area overheads. The benchmark circuits are locked using variety of scan-blockage based logic locking schemes. Finally, the proposed work is compared with the state-of-the-art Trojan insertion attack against scan-blockage based logic locking.