Area and Delay Efficient RNS-Based FIR Filter Design Using Fast Adders and Multipliers
M. Balaji, N. Padmaja · International Journal of Electrical and Electronics Engineering · 2023
Speed and area are the primary design concerns in today’s digital age. Increasing the rate at which multiplications and additions are performed has always been necessary for developing cutting-edge technologies. Wallace and Dadda multipliers are among the fastest multipliers used in many processors to accomplish fast arithmetic operations. A novel approach to design a Lookup Table (LUT) multiplier and adder was proposed and implemented in the Finite Impulse Response (FIR) filter. To improve the Residue Number System (RNS) based FIR filter’s performance, several adders like Carry Look Ahead (CLA) adder, Kogge Stone Adder (KSA) and proposed adder architectures have also been implemented. Compared with the 16 taps with 32-bit proposed adder with LUT multiplier, the hardware resource utilization (Logic Elements) is decreased by 5.97% and in 32 taps with 16-bit combination, it reduces by 7.60%. Compared with 32 taps with 4- bit word length, the proposed adder with LUT multiplier in the highlighted combinations, the Fmax is increased by 19.28% and in 32 taps with 16-bit, it increases by 29.74%. The Low-pass RNS FIR filter is designed for a cutoff frequency of 50 Hz, generated filter coefficients in MATLAB, and implemented to denoise the ECG signal.