Insights from Preliminary Analysis of Local Cache Performance in COTS RTOS for Multi-Core Processors
William Vance, Michael Mott, Mark Wotell, Tuan Bui, John Ross · 2023
Many avionic software platforms are built utilizing commercial-off-the-shelf (COTS) computer processors and real-time operating systems (RTOS). It is essential to the proper function of these platforms that the hardware and software on which they are built meet the necessary performance criteria and are certified to an appropriate level of airworthiness. Recent advances in technology have allowed the commercial market to transition from computer processors with a single processing unit in favor of multi-core processors (MCPs) that contain multiple processing units (cores) running in parallel. As a result of this transition, embedded computer solutions have seen significant gains in average-case performance while simultaneously seeing a reduction in size, weight, and power (SWaP).The advantages of MCPs may be diminished for avionics. The presence of interference among executing cores due to shared common resources complicates the development and assurance of robust, deterministic software. Since the technology is relatively new, the methodology for addressing these MCP-specific concerns in a safety-critical system is still not well-defined. The existing approach to the software safety process must evolve to incorporate the identification, verification, and mitigation of multi-core related interferences.In support of this effort, this paper describes a detailed process for analysis of local cache utilization on an MCP, and how to identify any potential cache availability or performance issues. The paper demonstrates how this process was used to detect an issue in the cache initialization process of an evaluation RTOS and target hardware board and analyze the resultant performance gains once the problem was corrected. These findings demonstrate why analysis is critical and should be performed early in the design phase of a system in order to verify the selected MCP and RTOS are performing as expected and/or intended. This approach provides immediate benefits to software applications running on a multi-core processor.