Reducing Reversible Circuit Line Count Using Boolean Techniques
Zaid Al-Wardi · 2023
Reversible circuits are essential for quantum computing and low-power digital design. However, designing reversible circuits with a low line count and minimal gate cost is challenging due to the inherent constraints of reversible logic gates. The two factors are known to be trade-offs, such that minimizing one of them is compromised with extended complexity in the other. The hierarchical synthesis approach of reversible circuits is scalable and usually results in circuits with relatively low gate costs but high line counts. In this paper, we propose a simple systematic hierarchical approach to reduce the line count of reversible circuits by utilizing Boolean techniques and properties of reversible logic gates. Our approach is designed to maintain the gate count with minimal increase while reducing the number of lines required for circuit realization. This reduction in line count offers significant improvements in circuit complexity. Therefore, our approach provides an efficient and cost-effective method for realizing reversible circuits.