Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express 6.0 and Compute Express Link 3.0
Debendra Das Sharma, Swadesh Choudhary · IEEE Micro · 2023
The sixth generation of PCIe (PCIe 6.0) specification adopted four-level pulse-amplitude modulation signaling at 64 GT/s for maintaining the same channel reach, cost, and power profile as previous generations. Lightweight forward error correction (FEC), a strong cyclic redundancy check (CRC), and link-level replay mechanisms deliver low latency, high bandwidth efficiency, and high reliability. Compute Express Link (CXL) uses PCIe 6.0 physical layer with latency-optimization mechanisms. Our nonpipelined implementation of FEC and the CRC is incorporated into PCIe 6.0 and CXL 3.0 specifications. We also propose a partitionable and pipelined implementation for FEC and the CRC for lowering gate count and latency. Synthesis results from the Synopsys Design Compiler demonstrates that for a 16-lane (x16) PCIe/CXL link partitionable to up to x4s, with four independent controllers using independently partitionable logic, we achieve a gate count of approximately 100,000 for the transmit and receive side with a FEC + CRC delay of less than 1 ns in each direction.