A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement
Xingyu Wang, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2023
This article presents a true random number generator (TRNG) that achieves high entropy generation across wide voltage and temperature (VT) range (0.3–1.0 V, −40 °C to 110 °C) in a single latch-based entropy source (ES). In the ES, static inverter selection technique to minimize the mismatch between the paired inverters, and noise enhancement methods to increase the root mean square (rms) of noise voltage ($\sigma _{n}$) are implemented for good randomness and robustness. In a 130-nm CMOS technology, the TRNG occupies 5343$\mu \text{m} ^{\mathrm{ 2}}$and consumes 0.116 pJ/bit at 0.3 V including an on-chip von Neumann post-processing circuit. The cryptographic quality of TRNG’s output is verified by National Institute of Standards and Technology (NIST) SP800-22 tests. Up to 325 mV$V$pp noise injection attack tolerance is confirmed by power supply frequency injection attack. And an equivalent 20-year life at 0.3 V, 25 °C is verified by accelerated NBTI aging test.