FPGA Partial Reconfiguration.
Michael Carrow · 2022
Problem Statement: Field Programmable Gate Array (FPGA) devices are very versatile, but they also have many limitations.Each FPGA has a limited number of programmable logic blocks, which can make it difficult to fit all of the desired logic into a design.In addition, the logic design is usually static after initial programming, and cannot be changed without resetting the whole device.This can be especially problematic in the event of a Single Event Upset (SEU) error, in which a radiation induced bit flip occurs in the FPGA's configuration memory, causing unwanted changes to the logic.