Validation and Test Challenges for Multi-Memory Bus BIST Engines
Armen Babayan · 2023
The most recent advanced technology nodes (e.g., FinFET, GAA) offer more possibilities to optimize MBIST timing for pre-inserted groups of memories with scheduling. Multi-Memory Bus BIST Engines - MMBBEs are developed to take advantage of these possibilities. The validation of a given MMBBE requires consideration of a diversity of multi-memory configurations connected to one bus. A huge number of such configurations hardens the overall validation. Currently there are no open sources related to the MMBBE validation methodology. The suggested approach allows to increase flexibly the validation coverage and to reduce an exhaustion during the validation. A design generation environment is developed for MMBBE validation basing on selection of primary/main parameters of the overall MMBBE specification characterizing presence or absence of a certain feature in the specification. A hierarchy of parameter sets is built charactering next groups of MMBBE parameters: secondary, ternary, etc. All values for some groups of parameters might be considered while the values for the rest of the parameters might be chosen randomly. The solution can be continuously improved via considering new SoC implementations and AI based methods including machine learning which will lead to natural changes in the hierarchy of parameters.