Design and Analysis of High-Speed Low-Power Dynamic Comparator
Kunal ., Anurag Yadav, Subodh Wairya · 2023
Now a days less power consumption and high-speed devices are need; therefore, there is a need to grow in the domain in which there is less trade-off between power and delay. A new topology of standard single-tail dynamic comparator (STDC) is presented in the paper. The comparison is done on the basis of delay, power, and PDP. The proposed comparator runs on clock frequency of 500 MHz. When compared with the previously defined STDC and standard double-tail dynamic comparator (DoTDC), this circuit gets less power consumption and delay. This is due to addition of a p-type metal oxide semiconductor (PMOS) transistor in the latch as well as in the amplification stage of the dynamic comparator. An 85% reduction in power and a 52% reduction in delay are observed after simulation. The proposed comparator works on the 90-nm technology. All the simulation results are carried out using CADENCE software at 90-nm technology. The total power dissipation is 54.891.IW and the delay is 107.10 ps.