Low Power Scan-based Built-in Self-test Based on True Random Number Generator Using Multistage Feedback Ring Oscillator
P. Suba, Arivazhagan, P., Stalin, A. · Mediterranean Journal of Basic and Applied Sciences · 2023
The gap between functional and test power consumption is growing bigger and bigger, with the latter reaching 2X to 5X of the former due to the ever-shrinking functional power and ever-increasing test power.Problems, such as excessive heat that may reduce circuit reliability, formation of hot spots, difficulty in performance verification, reduction of the product yield and lifetime, and so on, have become severe.A fast simulation approach was proposed for low-power (LP) off-chip interconnect design.An important through silicon via (TSV) modeling/ simulation technique for LP 3-D stacked IC design.Furthermore, the power dissipation of scan-based built-in self-test (BIST) is much higher than power dissipation in deterministic scan testing due to excessive switching activities caused by random patterns.Therefore, it is essential to propose an effective LP BIST approach.However, many of the previous LP BIST approaches cause fault coverage loss to some extent.Therefore, achieving high fault coverage in an LP BIST scheme is also very important.Weighted pseudorandom testing schemes and methods can effectively improve fault coverage.However, these approaches usually result in much more power consumption due to more frequent transitions at the scan flip flops in many cases.Therefore, we intend to propose an LP scan-based pseudo random pattern generator (PRPG).Bit-Swapping LFSR and Scan-Chain Ordering [1] describes Novel Technique for Peak-and Average-Power Reduction in Scan-Based BIST.This paper presents a novel low-transition linear feedback shift register (LFSR) that is based on some new observations about the output sequence of a conventional LFSR.The proposed design, called bit-swapping LFSR (BS-LFSR), is composed of an LFSR and a 2 × 1 multiplexer.When used to generate test patterns for scan-based built-in self-tests, it reduces the number of transitions that occur at the scan-chain input during scan shift operation by 50% when compared to those patterns produced by a conventional LFSR.Hence, it A B S T R A C T A new low power scan-based built-in self-test (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding.A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministic BIST.During the pseudorandom testing phase, an LP weighted random test pattern generation scheme is proposed by disabling a part of scan chains.During the deterministic BIST phase, the design for testability architecture is modified slightly while the linear feedback shift register is kept short.In both the cases, only a small number of scan chains are activated in a single cycle.Sufficient experimental results are presented to demonstrate the performance of the proposed LP BIST approach.This Proposed design will be implemented by Verilog HDL and simulated by Modelsim Tool.