A Practical Computer Architecture Education with RISC-V and TL-Verilog
Petar Minev, Valentina Kukenska, Ilian Varbov, Matyo Dinev · 2023
The report presents a hands-on learning approach that can be implemented in the Computer Architectures labs. A model of a pipelined microarchitecture RISC-V processor core developed using the high-level hardware description language TL-Verilog is described. Basic steps for implementation and visualization of the model are proposed. The necessity of its application in the educational process of students with different training profiles is substantiated.