Design of Accuracy Configurable Booth Multiplier using Sorting based Compressors
K Jason, P. Arivazhagan, P. Arunkumar · Irish Interdisciplinary Journal of Science & Research · 2023
There are different types of multipliers used in computing, but we use booth multipliers because we can perform signed multiplications, and we can perform partial product reduction using modified booth encoding algorithms.Approximations are used here to reduce the area, the power and the delay in an architecture like signal and image processing application where there would be a need for more adders or multipliers and to reduce the hardware complexity.This approximate booth multipliers are used in error tolerant application.The Reconfigurable multipliers can be dynamically reconfigured during run time according to the accuracy requirements of the application [1][2][3][4][5][6][7][8][9].Approximate computing is a promising approach to designing energy-efficient digital systems, as it allows for the tolerance of loss of quality or optimization in calculated results.'Approximate Computing: An emerging paradigm for energy-efficient design' discusses recent advances in approximate arithmetic block design, error and quality measurements, and algorithm level techniques for approximate computing [10].Speculative adders reduce critical path delays to sub-logarithmic delays by harnessing the tradeoffs between reliability and performance.The design of reliable variable latency adders combines speculative adders with error correction to achieve high performance for low area overlay compared to traditional adders.The authors describe Speculative Carry Select Adders (SCSA), a new function speculation technique to design low error rate speculative adder and low overhead, high performance, reliable variable latencies adders [11][12].The authors propose a low-error, reduced-width Booth multiplier that uses the right compensation vector based on input data.The design results show that both the gate count and key path delay of these new reduced-width multipliers are 50.94% and 66.04%, respectively.They also create a module generator based on their proposed architecture that generates C code and Verilog codes for each of the reduced width multipliers [13][14][15][16][17][18][19].A B S T R A C T An approximate computing technique has been applied in recent years to develop low-power design solutions for fault-tolerant applications.Since an application's accuracy requirements can change dynamically at runtime, it is necessary to design reconfigurable approximate circuits with varying power requirements proportional to computational accuracy.In this work, a new approximate booth multiplier circuit capable of accurately reconfiguring compressor based on sorting network has been designed.4:2 compressor-based sorting network that minimizes propagation path delay during partial product reduction.The design involves partial error correction through the addition of sign bits in a broken array multiplier.The design space of the 16-bit broken array multiplier, sign included, is deeply analyzed to include only non-redundant precision modes.The horizontal and vertical breaks introduced into the booth multiplier circuit are controlled by external control signals stored in the ROM.The proposed reconfigurable multiplier provides significant power savings compared to state-of-the-art accurate multiplier circuits and precision configurable multiplier designs.The proposed ACBAM multiplier using a classification network achieves 57.81% efficiency in area and 68.61% efficiency in latency compared to the current system.