An Efficient Reversible Universal Shift Register with Minimal Quantum Cost
Swathi Mummadi, Gnaneshwara Chary Udari · 2023
This paper introduces an innovative and highly efficient 4-bit Reversible Universal Shift Register (RUSR) design that employs reversible logic gates. The RUSR is capable of performing shifting operations, including left shift, right shift, and parallel load, akin to conventional CMOS-designed universal shift registers. In this study, we focus on the creation of a 4-Bit RUSR using a combination of a reversible Master-Slave D-Flipflop (RMSDFF) and a reversible 4X1 Multiplexer (RMUX41). The design of the RMSDFF and RMUX41 incorporates the use of Feynman (FG), Fredkin (F), and Modified Fredkin (MF) gates. Notably, the Modified Fredkin gate plays a pivotal role in optimizing the proposed architecture. The efficacy of our proposed architecture is demonstrated through key metrics such as garbage outputs (GO) and quantum cost (QC). Our architecture excels in terms of reduced power consumption, minimal quantum cost, and a decreased number of reversible logic gates and garbage outputs. As a result, this design holds significant promise for applications in quantum computing, Low-power CMOS design, and various other domains. The implementation of the RUSR in this paper relies on the utilization of the proposed RMUX41 and RMSDFF. These components are constructed using reversible logic gates and described in the hardware description language Verilog. The validity of our design is affirmed through rigorous verification with simulated results, employing the ModelSim Altera tool.