A 16nm 128kB high-density fully digital In Memory Compute macro with reverse SRAM pre-charge achieving 0.36TOPs/mm2, 256kB/mm2 and 23. 8TOPs/W
Weijie Jiang, Pouya Houshmand, Marian Verhelst, Wim Dehaene · 2023
Digital in-memory compute (DIMC) is recently gaining strong attraction due to its robustness against variability, and ease of integration into the digital design flow, compared to analog in-memory compute. However, most published DIMC macros suffer from low area efficiency, due to their need to modify the bit-cell and integrate the MAC operation into the storage unit, preventing the DIMC designs to upscale to large macros for practical tasks. This paper therefore proposes a DIMC macro that uses unmodified 6T bit-cells with added multiply and accumulate (MAC) logic on the bit-line. The energy penalty due to increased bit-line loading is alleviated with two techniques: 1) a weight stationary dataflow with charge reuse on the bit-lines across multiple operations; 2) a reverse pre-charge scheme to further limit the read energy. Experimental results show that the proposed macro achieves 23. 8TOPs/W for 8b MAC operation and storage density up to 256kB/m$\mathrm{m}^{2}$, enabling upscaling to large DIMC arrays.