Energy Efficient Approximate Floating Point Divider
J Namratha Nadh, Ayesha Sk, Sreehari Veeramachaneni, Noor Mahammad Sk · 2023
This work proposes a novel approach to designing an approximate floating point divider with an error percentage lesser than one percent. The proposed design is derived from the mantissa division analysis. Subtracting the lower 16-bits of the mantissa rather than dividing it and the rest of the most significant 8-bits are divided using standard division hardware will guarantee less than 1% error in output compared to the existing dividers from the literature. The proposed design saves energy 99.61% and 32.18% than the conventional floating point divider and approximate FPAD, respectively. The proposed design does not use any look-up mechanism and error correction circuits.