Power-Efficient and Programmable Hashing Accelerator for Massive Message Processing
Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Thi Hong Tran, Yasuhiko Nakashima · 2023
Ensuring security in modern domains such as blockchain and IoT requires developing hashing hardware that is low-power, high-performance, and flexible with massive message processing ability. However, existing configurable hashing architectures pose a challenge in processing a large amount of message input with high hardware efficiency and performance. Therefore, this paper proposes a power-efficient and programmable hash accelerator (P2HA) to achieve high flexibility and process large amounts of message input with high hardware efficiency and high performance. Three novel techniques are proposed to achieve those goals, including a one-dimensional reconfigurable 4×8 processing element array (PEA), a low-cost configurable arithmetic-logic unit (LC-ALU), and a massive message processing mechanism. The correctness of P2HA has been verified at the system-on-chip (SoC) level on the Xilinx Zynq UltraScale+ MPSoC ZCU102. We also provide the quantitative analysis and comparison with real-time results on the ZCU102 FPGA, which show that the performance of P2HA is 4.4-10.9 times faster than ARM Cortex-A53 CPU in hash computations of a large number of messages. Furthermore, comparison results on ASIC show that P2HA outperforms state-of-the-art works by 4.8-26.4 times in throughput, 7.3-59 times in area efficiency, 1.4-17.4 times in energy efficiency, and 7.1-84 times in EDP.