Low power and low area multiplier and accumulator block for efficient implementation of FIR filter
J. L. Mazher Iqbal, G. Narayan, T. T. Manikandan, M. Meena, Jose Anand · 2023
In communication system applications, the need for efficient design and implementation of the finite impulse response (FIR) filter is essential. Realization of such a filter with high bit width is a challenging task. The multiplier and accumulator blocks of the FIR filter take more delay, power, and area. In this chapter, the design of the FIR filter using the efficient multiplier and accumulator blocks is presented. We propose to use operations such as right shift, left shift, and carry save adder to develop the FIR filter. The multiplication and division are performed using the right shift and left shift operations. The FIR filter using the modified constant shift method (MCSM) multiplier block instead of a conventional multiplier is proposed. The modified multiplication decreases the quantity of hardware, power consumption, and surge the performance of the filter architecture. The FIR architecture is implemented using Xilinx Vivado. The parameter such as the look-up table (LUT) count, slices, flip-flops, power, and speed are analyzed with respect to existing filter architectures. Thus, the proposed novel filter architecture is implemented with high speed, less area, and less power.