A Novel Asynchronous Network-On-Chip Based on Source Asynchronous Signaling
Venkata Nori, Baudouin Chauviere, Mackenzie J. Wibbels, Kenneth S. Stevens · 2023
The communication subsystem of a system-on-chip(SoC) has been an exciting research area for more than three decades. With benefits ranging from increased power efficiency to better area utilization and scalability, networks-on-chip have seen an increased role in SoCs. Multi-core SoC architectures containing discrete functional units like GPUs and applicationspecific units are becoming increasingly popular, and in this, networks-on-chip play a critical role. Source Asynchronous Signaling (SAS) is a credit-based communication protocol that supports arbitrarily large but finite latency on communication links. The bandwidth and handshake frequency of this protocol are independent of wire latency. The work presented in this paper explores a new asynchronous network-on-chip (NoC) that utilizes SAS. First, we investigate the advantages of using SAS in NoCs. Then, we present a design method for building a deadlock-free NoC employing this protocol. Finally, we evaluate the power and performance numbers of this NoC using accurate simulation models in a torus architecture, and we compare it with a similar asynchronous NoC.