MBIST Area & Test Time Optimization Using Machine Learning
Darakshan Jamal, Ratheesh Thekke Veetil · 2023
In System-on-Chip (SoC) designs, a significant portion of the die area is allocated to Design for Test (DFT) logic, with a substantial fraction dedicated to Memory Built-in Self-Test (MBIST) functions. This results in significant per-part test costs, impacting the overall chip cost. To increase profit margins and achieve cost savings, it is crucial to optimize the MBIST area while balancing test time and considering physical design challenges. The exploration of different memory groupings, MBIST strategy and their associated physical design challenges can be a time-consuming task. Due to resource and schedule constraints, conducting multiple iterations during the project execution to arrive at optimal MBIST design becomes impractical. In this paper, we propose the use of machine learning (ML) algorithms to address the optimization of memory grouping and MBIST strategies. By leveraging ML models, we aim to identify the most suitable memory grouping and MBIST strategy that results in an optimized MBIST design. We can achieve better physical design metrics by applying the proposed ML model to generate RTL, including improved timing, reduced congestion, and a smaller area footprint. Overall, our research demonstrates the potential of ML algorithms in optimizing the MBIST area and test time, leading to significant cost savings and improved profit margins in SoC designs.