Design of a Fault-Tolerant Pseudo-3D Routing
Biswajit R. Bhowmik, N Gagan · 2023
A network on chip (NoC) exposes faults that disturb overall performance. Subsequently, a routing algorithm with fault tolerant facility has become a holistic aspect of reliable NoC communications. We propose a routing mechanism including fault tolerance in channels of a pseudo-3D mesh NoCs. The concept of a detour path is the foundation of the proposed solution. Its goal is to ensure the delivery of almost all packets with a detour of a few without utilizing broken or faulty communication functionalities. On evaluations, the suggested technique produces 11.47% greater throughput, 38.38% lesser latency, and 65.50% improved energy consumption compared to the baseline mesh NoC. Based on the findings, one may conclude that the proposed fault-tolerant routing performs more effectively even at higher traffic load levels.