A Novel Approach to Identifying Scan Issues During RTL Validation
Alli Sravan, Malagiri Shashi Vardhan Reddy, V.S. Nithin, Ravathkar Ashwin Kumar · 2023
As we know, today's system-on-chip designs are complex with billions of transistors on it making it very difficult to test. A module may behave properly in terms of its functionality during the designing of the chip, but it also should be ensured that every module in SOC must function properly in post-silicon. As the process of manufacturing requires fine precision, the chip must undergo testing during its designing phase. As a part of testing in SoC, it's of utmost importance to insert DFT (Design for Testing) components into all the IPs and the modules present in the SOC. Each soc can have hundreds of partitions and contain thousands of flops. During scan insertion, these flops are converted into scan flops to perform scan-based testing to increase the controllability and observability on the internal nodes of the circuit. During the conversion of flops into scan flops by ATPG, some of the non-scan flops which are part of critical signals such as Power switches, PLLs, Resets, etc., may also get converted and become part of the scan. In ATPG, validation happens at the partition level and these critical signals are provided with cut points. So, any toggle in the power switches will not affect the ATPG simulations. In soc, any glitch at the input of the clocks may cause the flops to capture an unsolicited value which may corrupt the power domain and PLLs may also lose their lock. These types of issues can be caught in full-level GLS where the design is very large and debugging these errors is a humongous task that is also at the very end of the cycle. In this paper, we discuss how to catch the issues mentioned above, early in the RTL cycle itself rather than going to the end of the cycle. By catching these issues, we reduce test cycle time, improve the quality of the chip, and hence reduce the cost of the chip.