Three Stage Comparator Design and Its Modified Version with Fast Speed & Less Kickback
International Research Journal of Modernization in Engineering Technology and Science · 2023
The three-stage comparator and its modified version, which increases speed and lowers kickback noise, are shown in this brief.The three-stage comparator in this study has an additional amplification stage in comparison to the conventional two-stage comparators, increasing the voltage gain and speed.The three-stage comparator allows for the use of nMOS input pairs in the regeneration stage and the amplification stage, further enhancing speed.This is in contrast to the conventional two-stage structure, which employs pMOS input pairs in the regeneration stage.Furthermore, a CMOS input pair is used at the amplification stage of the proposed modified version of the three-stage comparator.By cancelling out the nMOS kickback through the pMOS kickback, this significantly lowers kickback noise.Additionally, it adds a second signal line during the regeneration step, which further boosts speed.Both the traditional two-stage and the suggested three-stage comparators are implemented in the same 120-nm CMOS process for straightforward comparison.According to measurements, the redesigned three-stage comparator increases speed by 64% and reduces kickback noise by ten times.This enhancement does not come at the expense of more input noise or referred offset.