A Survey of Chips Security Technology Based on Scan Chain
Jing Zou, Zhikuang Cai, Xun William Xu, Hang Yang, Yufeng Guo · 2023
Scan chain insertion is a widely used technique in design for testability (DFT), which brings high fault coverage, good controllability and observability to chip testing. But for the encryption chip, the attacker can use the scan chain to carry out side channel attack on the chip, and leak the encrypted data in the chip. In order to ensure the security of the chip, scholars in this field have done a lot of research. They exposed the attackers against the AES hardware encryption algorithm attack methods, and put forward a series of corresponding security countermeasures, such as complex DFT structure, modify scan chain structure, scan I/O restriction and so on. In this paper, we deeply analyze and summarize the attack methods and security countermeasures commonly used at present, compares their advantages and disadvantages and limitations, and briefly analyze the development of secure DFT technology in the future.