Implementation of A Real-Time Lossless JPEG-LS Compression Algorithm Based on FPGA
Xinyi Dong, Peng Li · 2022
In order to balance image compression ratio, image compression quality and image processing time, an FPGA-based image compression system is proposed. The LOCO-I / JPEG-LS algorithm aims to provide lossless compression ratio, and reduce the overall complexity of the compression algorithm. In this work, the maximum compression ratio can reach 16:1 and average compression ratio can reach 2.61:1 for different input image streams. The maximum operational frequency of the proposed work can reach 103 MHz. Previous FPGA/ASIC-based JPEG-LS compressors bring forward optimization road maps. It is to use pipeline optimization techniques such as forward and look-ahead to split the context update loop, shorten the critical path to increase the clock frequency [1]–[4]. This road map fully explores the pipelining of JPEG-LS but ignores its parallelism potential, which limits the performance at 1 pixel per cycle (PPC). After implementing the algorithm into a Xilinx xc7k70tfbv676-3 FPGA demo board, we propose a new architecture that can process an average of 4 pixels per cycle.