A Novel Method to Achieve High Efficient Iteration of MBIST Pattern
Minqiang Peng, Keqing Ouyang, Feilong Pan, Guohua Zhou, Lei Chen · 2023
This is a common method to insert BIST logic in the chip for detecting memory faults during production. Power consumption and dynamic voltage drop (IR_drop) are the two obstacles limiting testing of all memories in a chip simultaneously with increasing area of memories. Current alternative method is to divide memories into several parts and test serially. However, it will take considerable time on group division and pattern iteration. In this paper, a novel idea is proposed to achieve high-efficiency iteration of MBIST pattern. With modified construction of mbist circuits, MBIST pattern was splitted into configuration part and main part. MBIST pattern could be updated easily by adjusting configuration, thus reducing the time of pattern iteration.