Design Optimization of Leakage Based PUF Circuit targeting at Ultra-Low Voltage Operation
Shunkichi Hata, Kimiyoshi Usami · 2023
PUF (Physically Unclonable Function) utilizing the physical characteristics of semiconductors has been attracting an attention as the LSI individual identification technology. This technology is expected to make it possible to authenticate genuine products and prevent the distribution of counterfeit products. On the other hand, IoT devices used in sensor nodes, are required to operate for a long period of time with limited power, so low power consumption is important. LRPUF (Leak Racing PUF) was proposed a leakage based PUF composed of digital circuits, but there is a problem of large power consumption. It has also been reported that PUF performance, such as uniqueness, uniformity and reliability, degrades significantly when operated at ultra-low voltages to reduce power consumption. In this paper, in order to improve the performance of LRPUF under ultra-low voltage, we propose an optimal LRPUF circuit for ultra-low voltage operation. By using design-of-experiments, we identified the PMOS gate width and body bias as high-impact factors on performance. Based an this finding, we conducted circuit optimization. Evaluation through simulation demonstrated that the proposed PUF achieved the uniqueness of 50.0%, the uniformity of 50.4%, and the reliability of 98.9% at the supply voltage 0.4V.