Cellular Automata Based 2D On-Chip Router for Power & Delay-Aware Operations
Trupti H. Nagrare, Abhay Ramakant Kasetwar, Rasika Bamnote, Mohammed Waseem Khanooni, Rahul Pethe, Sagar Pradhan · International Journal of Electrical and Electronics Engineering · 2023
In recent years, with the increasing demand for high-performance computing systems, there has been a growing need for developing on-chip communication systems that provide fast, efficient, and power-efficient communication. The design of cellular automata (CA) based 2D on-chip router is proposed in this study, which aims to address both power consumption and delay issues in on-chip communications. The proposed design utilizes a CA-based routing algorithm, which provides a simple and scalable solution to manage the routing paths in on-chip networks. The router architecture incorporates power and delay-aware optimization techniques to reduce power consumption and latency. The router has been designed and implemented in Verilog HDL and evaluated on an augmented set of Xilinx Virtex-7 FPGA platforms. The proposed on-chip router can be utilized in various applications, such as multi-core processors, network-on-chip architectures, and fieldprogrammable gate arrays. The router’s power and delay optimization features make it suitable for high-performance on-chip communication applications while minimizing power consumption and latency. The proposed cellular automata-based router outperforms the traditional router in terms of delay, energy, and throughput while occupying a smaller area. Specifically, the cellular automata-based router has 50 ns delay, 5 mJ energy consumption, and 5 Gbps throughput, occupying an area of 1000 um2 . In contrast, the traditional router has 100 ns delay, 10 mJ energy consumption, and 3 Gbps throughput, occupying an area of 2000 um2 for different use cases. Furthermore, the proposed technique performs best in throughput (4 Gbps) and worst in area (2200 um2 ).