Secure Data Transmission using Hybrid Crypto Processor based on AES and HMAC Algorithms
S. Umamaheswari, N R Vishal, N R Pragadesh, S Lavanya · 2023
In today's digital age, vulnerabilities in digital platforms have become a major concern, as cyber-attacks can lead to significant financial losses and privacy breaches. Encryption and authentication algorithms, such as AES and HMAC, are commonly used to secure digital platforms. However, running these algorithms in software can burden the CPU, leading to inefficiencies and potential security vulnerabilities. In this proposed paper, the implementation of a crypto-processor based on AES and HMAC to address the inefficiencies of software-based encryption and authentication. Our implementation uses AES for encryption and HMAC for integrity and authentication. By implementing these functions in hardware, we achieve greater efficiency and security, while reducing resource consumption and power usage. Our proposed crypto-processor design provides an efficient and secure solution for digital platform security, improving the overall performance of cryptographic operations. We demonstrate the effectiveness of our design through a comparison with software-based implementations of AES and HMAC, showing that our design provides a significant improvement in terms of throughput, latency, and power consumption. Our research contributes to the ongoing efforts to improve the security and efficiency of digital platforms, helping to protect sensitive data and ensure the privacy of users. Our proposed crypto-processor design provides a cost-effective and scalable solution for securing digital platforms, making it suitable for a wide range of applications in both commercial and government sectors.