Anomaly Behaviour tracing of CHERI-RISC V using Hardware-Software Co-design
Michal Borowski, Chandrajit Pal, Sangeet Saha, Ludovico Poli, Xiaojun Zhai, Klaus Dieter McDonald-Maier · 2023
Capability Hardware Enhanced RISC Instructions (CHERI) is an extension of conventional ISAs with capabilities enabling fine-grained memory protection. Recently, RISC-V ISA has been extended to CHERI-RISC-V (aka Flute) with additional support for CHERI. In this paper, we have proposed a lightweight continuous monitoring system (CMS) based on hardware-software co-design that communicates with the RISC -V to identify any abnormalities in its operational behaviour. The digital hardware of the functionality of CMS and the CHERI Flute RISC-V has been prototyped in the FPGA. The CMS extracts the different features from RISC-V and transmits them to the processing system via an API. Further, an anomaly detection program is being executed by the ARM processor residing in the PS portion of the ZYNQ. This program enables continuous evaluation of the system operation to spot hardware failure or unusual system behaviour. Finally, the complete design has been prototyped and verified on Zynq FPGA ZC706.