FPGA based Fault Analysis for Encrypted Code
S. Karunakaran, A. Rahul Kushal, M. Rashmitha, T. Dharshana · 2023
Currently, there is a lot of data being produced due to the proliferation of internet-connected devices and applications, making it increasingly difficult to safeguard and maintain privacy. In addition, the network now includes numerous devices with limited resources, thanks to emerging technologies like the Internet of Things. To tackle this issue, trustworthy cryptographic techniques must be used, and they must be efficiently implemented on resource-constrained devices. To protect wireless networks, hardware implementations of cryptographic techniques are common. These implementations offer strong security performance while minimizing processing and energy costs. However, they are vulnerable to side-channel attacks, unlike conventional systems. Particularly, fault attacks have demonstrated their effectiveness in cracking various strong hardware-based symmetric and asymmetric encryption techniques. Typically, FPGAs cannot incorporate a limitless number of logical resources into a single package, and design optimizations are necessary to achieve optimal performance and resource efficiency within these constraints. Using VHDL, an artificial neural network (ANN) can be implemented on an FPGA.